Rich Freeman on 24 Aug 2016 12:32:31 -0700

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On Wed, Aug 24, 2016 at 3:05 PM, Matt Mossholder <> wrote:
> I thought that was only true in muti-chip Opteron setups.  Since the memory
> controller is integrated into the CPU, you need to talk CPU-to-CPU to get at
> memory that is attached to the other CPU's memory controller...

It is possible.  I'd have to read up a lot more on how HyperTransport
works.  I thought that in a 4-core HT chip that the memory existed on
two different busses, with two cores on each bus.  Access to the other
bus involved some kind of locking or communication with the other
memory controller.

But, it has been a long time since I've seen those discussions.  I'd
have to read up more.

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