Re: [PLUG] RAID6 or RAID5+HS?

I had to go check some block diagrams and wrote to an EE at AMD to be sure. None of AMD's single-socket systems have been NUMA, even the multii-core systems had a single memory controller per socket. Even when in the unganged dual channel mode on the older chips, it was one memory controller per socket.

AMD's internal definition of NUMA specifically calls for multiple memory controllers. Having to communicate to a peer core doesn't make it NUMA, since it's generally cache-to-cache communication, core-to-system won't go through another core, it'll just go over the internal ring bus to the memory controller. NUMA means I talk on my ring bus to the HT link which talks to your HT controller, to your core-and-caches, or alternately to your memory controller (but never both in a single transaction), then the reply comes back the same way.

So core-ring-HT-ring-mem is a NUMA operation according to AMD, but core-ring-mem is not.

I think we're all deeply into semantics here, though.

On Wed, Aug 24, 2016 at 3:59 PM, Rich Freeman <r-plug@thefreemanclan.net> wrote:

On Wed, Aug 24, 2016 at 3:46 PM, Keith C. Perry
<kperry@daotechnologies.com> wrote:
>
> The main point is that NUMA is about about processors, not cores and there are "server" boards that can make use of real NUMA nodes. Cool stuff to play around with especially in the context of CPUsets, cgroups and other container or VM tech.
>

A core IS a processor, it just may or may not share some components
like a memory controller with other cores. My understanding is that
AMD processors typically operate in unganged mode, with different
cores having direct access to different memory channels. However, I'm
not sure that Linux takes advantage of this.

--
Rich
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