Rich Freeman on 25 Aug 2016 06:38:35 -0700

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On Thu, Aug 25, 2016 at 2:12 AM, Rich Mingin (PLUG) <> wrote:
> I had to go check some block diagrams and wrote to an EE at AMD to be sure.
> None of AMD's single-socket systems have been NUMA, even the multii-core
> systems had a single memory controller per socket. Even when in the unganged
> dual channel mode on the older chips, it was one memory controller per
> socket.
> AMD's internal definition of NUMA specifically calls for multiple memory
> controllers. Having to communicate to a peer core doesn't make it NUMA,
> since it's generally cache-to-cache communication, core-to-system won't go
> through another core, it'll just go over the internal ring bus to the memory
> controller. NUMA means I talk on my ring bus to the HT link which talks to
> your HT controller, to your core-and-caches, or alternately to your memory
> controller (but never both in a single transaction), then the reply comes
> back the same way.
> So core-ring-HT-ring-mem is a NUMA operation according to AMD, but
> core-ring-mem is not.
> I think we're all deeply into semantics here, though.

Well, there is no point in arguing over semantics, and everything
you've written is really helpful.  There is a dearth of information
online on this topic, surprisingly.

My question is this:  When you're using the unganged dual channel
mode, is the time required for any core to access any memory address
the same?  To me that is really the practical definition of NUMA.  If
the core will wait longer for a fetch depending on which address is
being requested, then there is a benefit if the OS keeps application
memory and core use local.  That is the whole point of NUMA.  You want
the kernel to know about the limitations of the hardware, so that it
doesn't just schedule processes on random cores and store its data in
random physical addresses.

Does AMD no longer use the unganged mode on its chips?  Or by "old" do
they mean everything but the stuff they're releasing next year that
everybody is eager to see?

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